IC3IoT 2018 | 15-17 February 2018

Workshop

FPGA Based System Design

Workshop Instructors:
Dr. J. Britto Pari, Assistant Professor, Department of ECE, Sri Sairam Engineering College
Ms. R. Chitra, Assistant Professor, Department of ECE, Sri Sairam Engineering College
Mr. K. Srinivasan, Assistant Professor, Department of ECE, Sri Sairam Engineering College
Ms. S. Saranya, Assistant Professor, Department of ECE, Sri Sairam Engineering College

Field Programmable Gate Arrays (FPGAs) provide an alternative solution for technicians and engineers looking to implement digital logic. FPGA basic structure can be modified into virtually unlimited number of times to perform a multitude of different missions by reconfiguring the hardware through software.
This course provides the participants with the basic knowledge of VLSI Design with an introduction to designing with Xilinx FPGAs using ISE development software tools. The course will allow all attendees to work towards successful implementation of teaching digital logic with FPGAs.

Key points and Features

  1. Knowledge about basics of VLSI.
  2. Overview of HDL.
  3. Better understanding of how to create a module.
  4. Analysis and synthesis of HDL design using Altera Quartus II
  5. Exposure to research opportunities in the proposed domain.
Advantages of FPGA Design
  • Faster time-to-market: No layout, masks or other manufacturing steps are needed for FPGA design. Readymade FPGA is available and burn the HDL code to FPGA.
  • No NRE (Non Recurring Expenses): This cost is typically associated with an ASIC design. For FPGA this is not there. FPGA tools are cheap.
  • Simpler design cycle: This is due to software that handles much of the routing, placement, and timing. Manual intervention is less. The FPGA design flow eliminates the complex and time-consuming floor planning, place and route, timing analysis.
  • More predictable project cycle: The FPGA design flow eliminates potential re-spins, wafer capacities etc of the project since the design logic is already synthesized and verified in FPGA device.
  • Field Reprogramability: A new bit stream (i.e.,program) can be uploaded remotely, instantly. FPGA can be reprogrammed in a snap while an ASIC can take $50,000 and more than 4-6 weeks to make the same changes. FPGA costs start from a couple of dollars to several hundred or more depending on the hardware features.
  • Reusability: Reusability of FPGA is the main advantage. Prototype of the design can be implemented on FPGA which could be verified for almost accurate results so that it can be implemented on an ASIC. If design has faults change the HDL code, generate bit stream, program to FPGA and test again. Modern FPGAs are reconfigurable both partially and dynamically.
  • FPGAs are good for prototyping and limited production. To make 100-200 boards it isn't worth to make an ASIC.
  • Generally FPGAs are used for lower speed, lower complexity and lower volume designs. But today's FPGAs even run at 500 MHz with superior performance. With unprecedented logic density increases and a host of other features, such as embedded processors, DSP blocks, clocking, and high-speed serial at ever lower price, FPGAs are suitable for almost any type of design.
  • Unlike ASICs, FPGA's have special hardware’s such as Block-RAM, DCM modules, MACs, memories and high speed I/O, embedded CPU etc inbuilt, which can be used to get better performance. Modern FPGAs are packed with features. Advanced FPGAs usually come with phase-locked loops, low-voltage differential signal, clock data recovery, more internal routing, high speed, hardware multipliers for DSPs, memory, programmable I/O, IP cores and microprocessor cores. Remember Power PC (hardcore) and Microblaze (softcore) in Xilinx and ARM (hardcore) and Nios(softcore) in Altera. There are FPGAs available now with built in ADC.Using all these features designers can build a system on a chip.
  • FPGA synthesis is much easier than ASIC.
  • In FPGA floor-planning can be done automatically, tool can do it efficiently.
Workshop outline
1. Introduction to VLSI Design
Over the past several years, Silicon CMOS technology has become the dominant fabrication process for relatively high performance and cost effective VLSI circuits. Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device. Before the introduction of VLSI technology most ICs had a limited set of functions they could perform. An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC designers add all of these into one chip.

2. Verilog HDL design based entry and simulation
This course will provide an overview of the Verilog hardware description language (HDL) and its use in programmable logic design. This topic emphasis the synthesis constructs of Verilog HDL. The participants will learn about some simulation constructs and gain basic understanding of Verilog HDL that will enable to create a design.

3. Altera signal tap analysis
Quartus® II software includes a system level debugging tool called SignalTap II that can be used to capture and display signals in real time in any FPGA design. During this course, the attendees will learn about: Probing signals using the SignalTap software. This course is aimed at the attendees who wishes to probe signals in circuits defined using the Verilog hardware description language. An equivalent tutorial is available for the reader who prefers the VHDL language.

4. Altera PLL mega function IP core
The Altera PLL megafunction IP core allows you to configure the settings of PLL.
Altera PLL IP core supports the following features:
  • Supports six different clock feedback modes: direct, external feedback, normal, source synchronous, zero delay buffer, and LVDS mode.
  • Generates up to 18 clock output signals for the Arria® V and Stratix® V devices and nine clock output signals for the Cyclone® V device.
  • Switches between two reference input clocks.
  • Supports both the adjacent PLL (adjpllin) and the C-Counter clock source (cclk) inputs to connect with an upstream PLL in PLL cascading mode.
  • Supports PLL output cascading.
  • Generates the Memory Initialization File (.mif) and allows PLL dynamic reconfiguration.
Workshop Outcomes
Attendees will be able to:
  • Understand the basics of VLSI Design.
  • Understand the origin of the Verilog HDL language
  • Use Verilog HDL building blocks (design units) including modules, ports, processes, and assignments
  • Model code styles including behavioural code style and structural code style
  • Understand the design methodologies of Verilog HDL and the differences between simulation models and synthesis models
  • Describe the general FPGA architectures and the design flow.
  • Interface between Altera software and DE1 FPGA Board.
  • Conduct System Verification and Troubleshooting.
  • Provide hands-on labs.


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